timing-diagram

Digital logic design tool and simulator

In this repository, I will be posting contents to learn about UML diagrams and practical examples for all the UML diagrams which I have designed using Lucid Charts

siggi creates a signal diagram from text

logi.js is a JavaScript library for working with Boolean algebra, logical expressions, truth tables, the Quine-McCluskey algorithm, timing diagrams, and more.

嘉立创EDA专业版扩展：时序图工具 - 基于 WaveDrom 的时序图绘制工具，支持在原理图中创建和放置专业的数字时序图。 EasyEDA proA timing diagram tool based on WaveDrom, supporting creation and placement of professional digital timing diagrams in schematics.

This repository is basic start of building your own processor using verilog (hdl).

Design a 4-bit ALU capable of performing 4 different arithmetic or logical operations using Quartus, implement it using Verilog HDL, and verify it using a timing diagram.

Interaktiver Simulator für digitale Logikschaltungen zum Lernen, Planen und weiterentwickeln mit Timing-Analyse, Race-Condition-Erkennung, FSM-Workflows und Verilog-/VHDL-Export. // Interactive digital logic simulator for learning, planing, and further development, with timing analysis, race detection, FSM workflows, and Verilog/VHDL export.